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SRAM controller in SOPC buil

Altera_Forum
Honored Contributor II
‎02-08-2010 05:38 AM
1,334 Views

Hi,  

 

Actually my project contains ISSI SRAM 512x16 bit. On my board there are two of these cascaded. While testing, I used the memtest code given in NIOS IDE. My hardware image contained NIOS processor, JTAG, onchip memory, tristate bridge and IDT controller (which I found having similar timing as my ISSI SRAM). The test was successful. My main confusion arose, when I probed the IC with CRO. I found that even when I had downloaded only sof file, there were some periodic pattern on pins of IC. Is it that controller in SOPC gives some periodic signals out? As I had expected no signal on pins till there was no software run. 

 

Regards, 

Saransh
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Altera_Forum
Honored Contributor II
‎02-08-2010 06:56 AM
635 Views

Where is the NIOS processor set to boot from? How do you know it's not running "code". It may be random junk. 

 

Jake
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Altera_Forum
Honored Contributor II
‎02-09-2010 05:26 AM
635 Views

NIOS processor is set to boot from onchip memory. I wanted to confirm whether the controller of SRAM keeps on sending some set pattern on its pins, even when software code is not running?

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