SRAM model Generation

[Altera_Forum]

Hello 

 I have a NIOSII system as follow : EPCS controller CPU - tristate-Bridge - sram_ctrl_v00 + some other bits   my SRAM is external to the FPGA. So I have created a controller sram_ctrl_v00 my sram_ctrl_v00 is an Avalon Memory Mapped Tri state Slave, describe in sram_ctrl_v00.tcl.   I found a model of the sram (in the enclosed zip file).   I don't really know how to include the model so it can be used with modelsim. (is it during create custom component ?...)   When I use eclipse , if I set all my code in SRAM , it will never generate the hex file associated with the SRAM (mem_init install or mem_init_generate). I would expect sram_ctrl_v00.hex   Can somebody help please ?   Regards   Ben

[Altera_Forum]

Hello , 

 Please I am facing the same problem can you give me some advice on interfacing external memory: I wrote a memory model+testbench+controller How should I move forward?  I would appreciate any advice...

[Altera_Forum]

Hello 

 The model need to be included in the file that represent your NIOS (at the bottom of the file). You will find locations where you can include your code : -- <Altera_Note>.....   The code will not be removed when you re generate your NIOS II system.   This is the idea.   To check my design , I had no time to perform what is described above, but this is the philosophy. Instead , I have used the internal memory under Modelsim , and use SDRAM in the real product.   This was to be able to check a full design (NIOS + Logic) together.    Also , you will have to set the NIOS II software/BSP (under Eclipse) to generate the correct file for SDRAM or Internal Mem.   Ben

[Altera_Forum]

Hi ben, 

 I also need to integrate a custom memory in my prjoject. But I don't have idea how the memory controller should look like. I already implemented the model and testbench for Cypress 1024x8 Bit memory. Can you please share me a piece of code to get an overview ?  Regards

[Altera_Forum]

What is the difference between the following code and the real sar controller? 

   --- Quote Start ---   library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;  entity sram1024kx8 is  port (A : in Std_logic_vector(19 downto 0);  D : inout Std_logic_vector(7 downto 0);  nCE : in std_logic;  nCE2 : in std_logic;  nWE : in std_logic;  nOE : in Std_logic); end;  architecture Behaviour of sram1024kx8 is  subtype Byte is Std_logic_vector(7 downto 0);  type Mem is array (0 to 1048576 ) of byte;  signal Memory: Mem := (others => Byte'(others=>'U'));    begin   process(A, D, nCE, nCE2, nWE, nOE)  begin  D <= (others => 'Z');  if nCE='0' and nCE2='0' then  if nOE = '0' then -- Read operation  D <= Memory(To_Integer(unsigned(A))) after 10 ns;  elsif nWE = '0' then -- Write operation  Memory(To_Integer(unsigned(A))) <= D;  end if;  end if;  end process; end;  --- Quote End ---    Please I can't get the relationship between the both I thought it was enough ? Do you have an example so that I could based on this ?