Hello.
I'm trying to build SR flip-flop with VHDL. Here is the code:
entity first is
port(s,r:in bit;q,nq:buffer bit);
end first;
architecture first_arc of first is
begin
nq<=not (s or q);
q<=not (r or nq);
end first_arc;
Very simple.
However, while inputs change through simulation time range (in vector waveform file), Quartus simulator returns all outputs zeros, with no regard to the inputs.
When I set the inputs to constant value through the simulation time, it works properly.
I've tried functional simulation as well as time simulation. I've got the same result.
What's the reason for such results?
