CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your
profile.
Hi: I generated a scatter-gather DMA ip in the sopc builder, and I want to learn the timing of the DMA IP, is there a way to generate a scatter-gather DMA IP simulation environment? thank you very much !
If interested, the pcie core comes with a sgdma example. Generate this testbench from ways and you will be able to see the dma timing. You will require to understand the built in bfm if you want it to do other things. The example can be found in the altera directory under ip cores. Hope this helps..
Sorry I wasn't clear, I meant the installation directory c://altera/ .. / quartus/ ip/ altera_pcie. Use sopc or qsys to generate the examples test bench. Let me know if that helps.
