Sequential Switching

[Altera_Forum]

I am trying to develop a sequencer digital circuit in VHDL and implement it on a DE 1 dev board although I have hit a wall. I have done a signal tap of the output of my FPGA although when I take a look at what actual comes out of the FPGA and it is different than the Signal Tap. Does anyone have a clue to as why this would occur? See both the signal tap and the digitzer signals. For reference Blue is clock, orange is TX1, purple is TX2, pink is TX3 and yellow is TX4.  

http://www.alteraforum.com/forum/attachment.php?attachmentid=11200&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=11201&stc=1

[Altera_Forum]

What have you set as the signal tap clock? 

Signaltap only shows tx/rx enable signals, not the actual tx/rx Where is the VHDL?

[Altera_Forum]

Did you check if you had a short circuit between TX2 and TX3? You can generate a simple FPGA project that drives both pins to different signals (for example 0 for TX2 and 1 for TX3) and check the output with the digitizer.

[Altera_Forum]

As for the signal I am using for a clock it is the input of my state machine and I will try to check out if there is a short between TX3 and TX4. For now I have attached my VHDL if you can find any errors in here.

[Altera_Forum]

My experience is the width shown in signaltap does not directly correlate to the actual signal. It is something expected that the TXs' pulses are of same width in your design? 

 Agree with Daiwen, you should check also if there is any short on the board.

[Altera_Forum]

Another thing to try out would be output the TX1 signal to TX2 pin to see if similar observation occurs? This can help to verify is short occur as well.