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Hi,
Please find attached the block diagram of LVDS transmitter and receiver as shown in device handbook of Cyclone V. LVDS transmitter contains serializer, which according to my understanding contains following 8 bit latch(D flip flops)--> 8b/10b encoder --> Parallel to serial converter Am i correct? If yes, kindly explain how in the attached figure instead of 8 bit data entering into a serializer, a 10 bit data (tx_in) is entering? 8b/10b encoder is a basic block of the serializer. I have searched online and have seen that a serializer always contains 8b/10b encoder So the data entering this encoder must be 8 bit. How it is 10 bit data that is sent to the serializer? Mishahttp://www.alteraforum.com/forum/attachment.php?attachmentid=11615&stc=1- Tags:
- Cyclone® V FPGAs
- lvds
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Hi Misha,
The LVDS serializer does not have 8b10b block. It is only the pure serializer. You will need to build your own 8b10b instance in core logic to work with the LVDS SERDES.
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