Seriallite on ArriaIIGX

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Seriallite on ArriaIIGX

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I want to implement 4 independant serial channels with SerialliteII.

When compiling the design I always get an error, because the compiler generates a new ALTGX-reconfig block for each channel, and so he wants to place the 4 channels in different ALTGX blocks, instead in the same.

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