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I am about to run an experiment of some digital audio processing on the Cyclone V based terasic Atlas / DE0-Nano-SoC kit, and I'm looking for an advice:
The audio processing IP is made solely in the FPGA fabric, and HPS/linux is only going to be used for setup, status and run-control. The linux application will have to set a block of 384 bytes of configuration into the FPGA fabric prior to start. The question is how to get the configuration into the FPGA fabric most simply, yet elegantly. No streaming to/from HPS, and changes to this configuration occurs very seldom. I plan to use PIO for the overall run and status control of the FPGA processing. For the 384 bytes of config, can this be a way to do it: Implement a dual-port RAM on the LW bridge and implement a FPGA FSM that fetches the configuration into the audio IP? Or are there other alternatives to do this?Link Copied
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