Hello,
I'm very familiar with the Xilinx ISE flow, and I know they allow component based design; where individual designers can create their own components, then integrate them together at later stages in the flow. In particular, Xilinx allows one to create a single ngc file, which is a technology independent implementation of a component. Using the ngc file, combined with a component wrapper (this is just a module declaration in verilog, or entity delcaration in VHDL), one can give your design for someone else to use.
What's the equivalent in Quartus? I remember hearing about their team based flows, but it's unclear to me what files you pass to the integration team to consolidate all the components together into one design. Would you simply give them your HDL? It would be nice if you could give them a partially synthesized netlist, or place-and-routed component, so the integration team can just plug the components together.
