Shift Register

Altera_Forum · ‎12-07-2010

Hi!

I am just trying to generate a shift register in verilog. Quartus 9.1sp2 provides me with an error message I don't understand:

"Error (10198): Verilog HDL error at stratixIII_3sl150_dev_niosII_standard.v(246): part-select direction is opposite from prefix index direction"

Any clues what I am doing wrong?

Code: (Line marked with * is where the error is reported)


//number of FFs 
`define WIDTH 10
module sreg(
<snip>
  
   //-**************************************************************************
// Generate Signal
//-**************************************************************************
   reg          genreg;
   always @(posedge clk or negedge reset_n)
     begin
       if (!reset_n)
         genreg = load_genreg;
       else
         genreg = ~genreg;
       end
   //-**************************************************************************
// Shift register
//-**************************************************************************
   reg   sreg;
   always @(posedge clk)
     begin
*     sreg = sreg;
       sreg   = genreg;
     end
   assign out = sreg;
endmodule

Altera_Forum · ‎12-07-2010

Assuming you copied and pasted directly from you HDL file you spelled "WIDTH" wrong on the right side. I don't use defined values myself so I don't know how verilog is supposed to behave in that case.

Altera_Forum · ‎12-07-2010

Gratulations for looking sharp! I didn't see it. Apparently, the Verilog preprocessor is assuming a value of zero for unknown symbols instead of complaining about a missing definition.

Altera_Forum · ‎12-08-2010

:oops: Yes, you are right. Seems that the error message misled me slightly. Thanks!

Altera_Forum · ‎12-09-2010

I tend to use local parameters for things like this, the same typo if it was a localparam I think would have resulted in a more meaningful error message. I don't know the pros and cons for one way or the other but I think we now know a con when using 'define :)

Anyway what that message means is that you had [-2:0] as the subscripts on the left side as a result of this verilog quirk.