Is there a reason SignalTap offloads acquisitions immediately after "Run Analysis" is requested, even when trigger conditions are not met? I tried removing and adding the *.SDC timing commands to meet Timequest Contraints (to no effect):
set_input_delay -clock 10.0 set_output_delay -clock 10.0There's not much to configure in Qsys for JTAG. The Nios II system is fed a 100Mhz clock, which I used as the trigger clock. Setting conflicting triggers (EOP and SOP both high, *all* signals to 0xFFFFF, no signals at all) seems to simply always trigger an acquisition. I'm trying a bunch of different things but to no avail. Hmmmmm....
What's your trigger condition set to, Basic AND or Basic OR? I assume AND, since that's the default, and it does sound strange. On my SignalTap, it doesn't download until the trigger occurs. (I am only doing one signal, so not helpful for a test case)
I have experienced two similar situations:1- The JTAG cable/programmer is faulty. In this situation, unexpected behavior is observed. Try testing another cable/programmer. 2- The signal clock domain is different from the SignalTap clock. In this situation the condition may trigger, but you observe that it should not.
Rysc, msj, and sstrell,Thank you all for the "magic dust". I really don't know why, but after a few weeks of having this problem and troubleshooting it's working again. During troubleshooting, I even pulled legacy designs and the standard Altera TSE Tutorial off of Altera University and they acted the same way and triggered no matter the trigger condition. Each time, the signals would have been in the same clock domain as the trigger clock. The only thing I changed just now was I opened up a second instance of Quartus/SignalTap, so that I had two running on my machine at the same time. I'm using the Altera USB Blaster with a DE2-115 Cyclone IV board. Perhaps it had something to do with the driver (as msj had mentioned), and it was fixed by opening up two instances of Quartus/SignalTap.