SignalTapII need to load .sof conflicts with earlier loaded .jic from EPCS.

[Altera_Forum]

Hello! 

Please advise how to use SignalTapII in the following situation. SignalTapII is to be used to test dataflow from PCIe card in the presence of a testing program. PCIe card's PCIe controller IP core is inside EPCS ( loaded from .jic in SFL ) and is loaded into Cyclone4GX during power up. After that PCIe card is recognized by its driver and the testing program can be used. SignalTapII has a built-in SOF manager to load .sof file, otherwise it doesn't work although the needed .sof is already inside Cyclone4GX after power up. If I load the .sof in SignalTapII, then it crashes the previously loaded ( from EPCS ) PCIe controller IP core and the testing program partially hangs the PC. Q: Is there a workaround for this situation?

[Altera_Forum]

Try the following; 

 1. Power-up your test machine containing the PCIe card, and stop at the BIOS screen.  2. Download your .sof and connect SignalTap II.  3. Escape from the BIOS and allow your PC to continue booting.  This ensures that the BIOS enumerates the PCIe core, and that you do not change the FPGA configuration after the PC boots.  Cheers, Dave

[Altera_Forum]

Do You suggest to use 2 PCs - one with the PCIe card and the testing program and another PC with Quartus+SignalTapII and the Download Cable? 

OK, thank You! Currently I have a single PC for all the thing together. Later I'll try it with the second PC with Quartus+SignalTapII and the Download Cable.

[Altera_Forum]

--- Quote Start ---  Do You suggest to use 2 PCs   --- Quote End ---   Yes of course. It makes no sense to debug hardware on the same machine that is running Quartus + SignalTap II.  Cheers, Dave

[Altera_Forum]

Hello, Dave! 

Your advise really helped!