Simple DDR input in Cyclone V

[Altera_Forum]

After spending the better part of the day RTFM, I have to ask:  

 Is there a simple way, that does not involve using the MegaWizard to create an ALTLVDS_RX, to implement a DDR input in a Cyclone V device? I mean, something as simple as Xilinx' IDDR2 primitive.   I have a source which provides some DDR data bits and a synchronous clock, and all I need to do is to capture the bits in the input and present two outputs (one rising edge, one falling edge) per data bit.  This should be incredibly simple ....  Thanks.

[Altera_Forum]

Your needs seem very simple, why are you messing with ALTLVDS_RX, it's typically used as a deserializer. Can't you just route each data bit to a pair of flip-flops, one clocked on the negative edge and the other on the positive edge?

[Altera_Forum]

--- Quote Start ---  Your needs seem very simple, why are you messing with ALTLVDS_RX, it's typically used as a deserializer. Can't you just route each data bit to a pair of flip-flops, one clocked on the negative edge and the other on the positive edge?  --- Quote End ---    Well, that's just it. I'm concerned about meeting timing. In the Xilinx world, there are input DDR flip-flops in the IOB, so the timing to both the rising and falling edge flops is the same and predictable.  How do you guarantee you meet setup and hold around both edges of the clock when the routing to the two flip-flops is in the fabric?   There is a drawing in the Cyclone V Device Handbook (figure 5-10: IOE Structure for Cyclone V Devices) which shows three input registers in the IOE structure. Two are connected to the input buffer (after a delay element), and they are clocked on opposite edges. The third flop follows the falling-edge flop and is clocked on the rising edge; this gets the bits from both edges of the clock onto the rising edge.  So the questions are:   a) can the synthesis detect that you are inferring those flops in your HDL and push them into the IOE, or if not, b) is there an element that can be instantiated, other than generating the ALTLVDS_RX with a deserialization rate of 2 (which bypasses the deserializer shift register)?  (It's bad enough that you can't use an incoming bit-rate clock with the ALTLVDS_RX to deserialize an incoming bitstream. What is up with that? You need a word-rate clock, from which a PLL is used to generate the bit-rate sample sample clock, and then if you want to deserialize 12-bit words, you're outta luck.)

[Altera_Forum]

Try ALTDDIO_IN

[Altera_Forum]

--- Quote Start ---  Try ALTDDIO_IN  --- Quote End ---    Ah, yes. I was searching for "DDR" and not "DDIO."