Hi ,
I would like to simulate a simple system using Altera Modelsim.
I followed the manual for "simulating Nios 2 embedded processor design" (
http://www.altera.com/literature/an/an351.pdf) .
Currently i have:
1. A simple verilog testbench including Nios2 , DDR3 controller and DDR3 memory model
2. "hello_world.c" software that i would like to compile and load to the ddr3 memory model.
The idea is that the Nios2 controller will fetch the commands from the DDR3 and execute the SW.
The manual recommends to run the simulation using the "run as" command from Eclipse.
I would like to know if i could bypass this by loading the compilation results to the DDR3 memory and run the simulation using Modelsim vsim command(like it was explained in the simulating qsys basic tutorials)
If anyone ever tried this i could use some support / example .
Thanks,
Ilan
