Hi everyone.
As you can all see i am new on this forum and i already start with a new thread. Actually i already saw some threads (like this one
http://www.alteraforum.com/forum/showthread.php?t=36918 )
that are a little similar to my question. But as i am new in verilog hdl i would like to ask about some help.
I have to simulate using matlab and design using verilog hdl in quartus ii a CIC filter. Because the band width of a single-stage CIC filter is fixed, in order to realize the desired band width, in this case 10KHz, i must calculate how many CIC filters should be cascaded. By the way, the main sampling frequency is 65MHz,and it is a very important parameter to be used in the design. The frequency domain ripple of the filter is not given, so you can set it in advance, like 0.1dB or 0.5dB
Can anyone please share some help to make this happen?
Thank you
