Simulation of ARRIA 10 FPLL & IOPLL phase shift

[Altera_Forum]

I am building a RGMII interface using the following IP blocks and some custom logic. 

1) Altera GPIO (setup as DDIO output with data width = 5 for data[3:0] & CTL). 2) Altera GPIO (setup as DDIO input with data width = 5 for data[3:0] & CTL).  3) Arria 10 FPLL (setup as follows:  a) FPLL Mode: Core  b) Ref clk = 125.0MHz  c) Bandwidth: medium  d) Operation mode: direct  e) Number of clocks: 2   Outclk0 :  a) desired freq: 125MHz  b) actual freq: 125MHz  c) phase shift units: degrees  d) phase shift: 0.0 degrees  e) actual phase shift: 0.0 degrees   Outclk1 :  a) desired freq: 125MHz  b) actual freq: 125MHz  c) phase shift units: degrees  d) phase shift: 60.0 degrees  e) actual phase shift: 60.0 degrees    My problem is that when I simulate the project I do not get the desired phase shift in the output clocks from the FPLL. The clocks are present but they are locked together (0 degrees phase shift). I can vary the clock speeds, add and remove clocks, etc... but I cannot get the phase shift. Being able to do what I can do makes me believe that I have all the pertinent libraries. I originally tried to use the IOPLL with no success. It had the same type of problem. I am aware of the IOPLL eratta and as such thought maybe that was where the problem lied so I moved to the "core mode" of the FPLL IP where it is able to drive the fabric.  I am using the following Aldec Simulation tool: Aldec Riviera-Pro 2015.10 64bit  I am using the following Quartus tool: Quartus Prime Version 15.1.1 Build 189 SJ Pro Edition Patch 1.04 installed   Has anyone successfully simulated one of the Arria 10 FPLL's (with defined phase shift) with the above tools or with any tool for that matter as long as it's in an Arria 10 and using the Quartus Prime software that I call out above.  thanks, david

[Altera_Forum]

Hello, hello, hello.... 

Is there anybody in there? Just nod if you can hear me. Is there anyone at home?

[Altera_Forum]

I share your frustration, David. This forum is a ghost town compared to the Xilinx user forum. I don't know if that's due more to lack of attention from Altera or just a general lack of customers actively working on Altera designs. We are also targeting Arria 10, in our case the Arria 10 SoC. We started in a Xilinx Zynq but ran into some limitations that made us take another look at Arria 10. The silicon looks great, but the Altera tools, the number of dev kits and reference designs to work with, the forum support, and the documentation are all way behind Xilinx. It's not even close. Altera better step it up or they will never ever be competetive with Xilinx again. 

 Sorry I can't help you with your problem, but I couldn't pass up an opportunity to vent a little. There could very well be a problem with the fPLL simulation model. You might try doing a gate-level simulation and see if it behaves any differently. Or if you have a dev kit available try it in the hardware and make sure it works there. Good luck.  Bob