Signal Tap not synthesized by Quartus 15.1

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I have new install Quartus Prime Lite edition on my Windows 8.1 machine. When I tried to use signal tap logic anayazer it produce the error below. I can not overcome this problem, so I can not use signal tap for debugging. 

 I have searched web for further information but I did not find any information about this problem.      --- Quote Start ---   Info (12033): Analysis and Synthesis generated SignalTap II or debug node instance "auto_signaltap_0" Info (11170): Start IP generation for the debug fabric within sld_hub. Info (11172): 2016.02.16.22:32:10 Progress: Loading slddc36993e/alt_sld_fab_wrapper_hw.tcl Error (11176): Set_instance_parameter_value: There is no parameter named DESIGN_HASH on instance alt_sld_fab Info (11172): invoked from within Info (11172): "set_instance_parameter_value {alt_sld_fab} {DESIGN_HASH} {67426ec0ff4f598c1b52}" Info (11172): (procedure "compose" line 3) Info (11172): invoked from within Info (11172): "compose" Info (11172): invoked from within Info (11172): "interp eval $slave { Info (11172): Compose Info (11172): }" Warning (11175): Alt_sld_fab.alt_sld_fab: This module has no ports or interfaces Error (11176): Alt_sld_fab.: version not allowed for EModuleProperty, must be in {[DESCRIPTION, NAME, VERSION, MODULE_TCL_FILE, MODULE_DIRECTORY, INTERNAL, HIDE_FROM_SOPC, HIDE_FROM_QSYS, HIDE_FROM_QUARTUS, OPAQUE_ADDRESS_MAP, GROUP, AUTHOR, ICON_PATH, DISPLAY_NAME, DATASHEET_URL, TOP_LEVEL_HDL_FILE, TOP_LEVEL_HDL_MODULE, INSTANTIATE_IN_SYSTEM_MODULE, EDITABLE, VALIDATION_CALLBACK, EDITOR_CALLBACK, ELABORATION_CALLBACK, GENERATION_CALLBACK, COMPOSITION_CALLBACK, PARAMETER_UPGRADE_CALLBACK, OUTDATED_IP_FILE, ANALYZE_HDL, STATIC_TOP_LEVEL_MODULE_NAME, FIX_110_VIP_PATH, SUPPORTED_DEVICE_FAMILIES, REPORT_TO_TALKBACK, ALLOW_GREYBOX_GENERATION, SUPPRESS_WARNINGS, STRUCTURAL_COMPOSITION_CALLBACK, NATIVE_INTERPRETER, PREFERRED_SIMULATION_LANGUAGE, REPORT_HIERARCHY, UPGRADEABLE_FROM]} Info (11172): invoked from within Info (11172): "set_module_property version 15.1" Info (11172): invoked from within Info (11172): "interp eval $slave { Info (11172):# (C) 2001-2015 Altera Corporation. All rights reserved. Info (11172):# Your use of Altera Corporation's design tools, logic functions and oth..." Warning (11175): Alt_sld_fab: This module has no ports or interfaces Info (11172): Alt_sld_fab: Generating alt_sld_fab "alt_sld_fab" for QUARTUS_SYNTH Info (11172): Alt_sld_fab: "alt_sld_fab" instantiated alt_sld_fab "alt_sld_fab" Info (11172): Alt_sld_fab: Done "alt_sld_fab" with 2 modules, 2 files Info (11171): Finished IP generation for the debug fabric within sld_hub. Info (12021): Found 1 design units, including 1 entities, in source file db/ip/slddc36993e/alt_sld_fab.v  Info (12023): Found entity 1: alt_sld_fab Info (12021): Found 1 design units, including 1 entities, in source file db/ip/slddc36993e/submodules/alt_sld_fab_alt_sld_fab.v  Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab Error (12154): Can't elaborate inferred hierarchy "sld_hub:auto_hub"   --- Quote End ---