Simulation with PCI Express created with Qsys in a sub-system

[BHOu6]

Hello,

I'm designing a system with PCI Express based on Cyclone V GT. I create firstly a qsys called "pcie.qsys" by using exemple design with pcie_cv_hip_avmm. And I create another qsys for my application called "app.qsys". And I create a "top.qsys" that contains these two sub-systems "pcie.qsys" and "app.qsys". All necessary interfaces of PCI Express are presents at "top.qsys". When I test "pcie.qsys" as top with testbench generated by Qsys, that works fine. But when I put it in "top.qsys" as a sub-system, that doesn't works any longer. I found that some BFM files such as altpcietb_bfm_driver_avmm.v, altpcietb_bfm_top_rp.v are not created when I use "pcie.qsys" as a sub-system. Someone has a idea for this?

[Nathan_R_Intel]

Hie, For Cyclone V PCIe simulation, if using the reference design from Cyclone V user guide, the file hierarchy cannot be changed, otherwise the simulation cannot run. This is because Quartus includes .tcl or do file to compile and load the necessary simulation libraries to run simulation. Hence, changing file naming and hierarchy needs to be done at the tcl file used to invoke simulation as well. Please refer to our user guide (Pg 2-4) on running simulation correctly. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avmm.pdf Do let me know if you have further questions. Regards, Nathan