Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Single Clock vs Multiple Clock, which approach is the best ?


Hi all, 

Its my first time to deal with FPGAs, I have a question about the clock signals. I know there is 2 options for clocking FPGA entire blocks .You can use one or more external input clocks to derive one or more PLL and/or Global clock network.

Using one input clock approach, I can generate all clock I need for all enabled blocks . Same with Multiple input clocks.

Which approach is the best ? is it depends on the application itself , performance , power consumption or another thing ? 

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Advantages of using PLL inside FPGA:

1) Lesser FPGA pins are required.

2) With PLL generated clocks, you can control the phase relationship with incoming clock as well as other generated clocks.

3) Wide range of frequencies can be generated and can also be changed anytime.

4) Board space is saved.

Disadvantage of PLL:

Compared to the advantages there are very less disadvantage.

1) Introduction of a small amount of jitter, but this is application specific requirement.

2) The FPGA PLLs usually work on high frequency inputs, ~5MHz or more. It cannot be used for slower clocks. Check individual device datasheet for that.

I would prefer one clock input and generated the others as required. This way, there is more control with FPGA designer and less burden on board designers.


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