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21615 Discussions

Single-port RAM output timing issue

Altera_Forum
Honored Contributor II
‎11-13-2014 05:43 AM
1,009 Views

I'm using ArriaGX, i found the single-port ram timing waveforms as below. The output should be valid in the next clock cycle. 

http://www.alteraforum.com/forum/attachment.php?attachmentid=9709&stc=1  

 

And in one of my projects, it works as above timing waveform, the signaltap image as below 

http://www.alteraforum.com/forum/attachment.php?attachmentid=9710&stc=1  

Above ram is small, and implemented by one M4K block. I have another project, which include a big ram that implement by 2 M-RAMs and several M4K. This big ram's output latency is more than above small RAM. It needs to wait one more clock cycle, as below 

http://www.alteraforum.com/forum/attachment.php?attachmentid=9711&stc=1  

 

BTW, these two rams are implement by same setting, except the port-width&depth difference. Is this because of M-RAM need longer latency than other small RAM cell (eg.. M512&M4K)?
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