Slew Rate settings

[NShan12]

Hello,

I am using Quartus Prime STD 20.1.1. The device is Cyclone 10 FPGA: 10CL080YU484A7G.

I see that in the pin planner there is only one option under Slew Rate settings as seen in the below screenshot.

The setting "2" gives fastest slew rate but for certain output pins I need slowest possible slew rate setting "0". How can I enable the slowest slew rate? 

Also, I see other settings such as "Near Capacitance" and "Toggle rate". Can I use these to further control the slew rate on the pins?

I could not find any documentation describing all the settings on FPGA IO pins. Please direct me to any resources available on these topics. The Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook does not discuss the meanings of all the IO configurable settings.

Thank you!

[Farabi · Accepted solution]

Hi, 

the slow slew rate is not supported by all IO standard set to the GPIO pins. You need to use the IO standard which supports slow slew rate and set this IO standard to the GPIO pin you want to use. 

If you see the IBIS model, the IO standard with 's' at the last of their name, is slow slew rate, 'm' for medium slew rate and 'f' for fast slew rate:

IBIS file for Cyclone 10 LP : https://cdrdv2.intel.com/v1/dl/getContent/674929

regards,

Farabi

[Farabi]

Hi, 

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

best regards,

Farabi