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LFrin
Novice
857 Views

Speed Transceiver-Channel near PCIe Hard IP Blocks

Hello,

 

I use the FPGA Cyclone V GT "5CGTFD7C5F23I7N".

 

I'm wondering if the speed of the transceiver channels next to the PCIe Hard IP Blocks is limited? Can these channels also be used as 5 Gbps transceivers?

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3 Replies
SengKok_L_Intel
Moderator
115 Views

You can refer to the following PCIe avalong ST user guide, page 52 to understand the Channel placement and limitation.

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avst.pdf

 

The answer should be "You can assign other protocols to unused channels the if data rate and clock specification exactly match the PCIe configuration"

 

Regards -SK

 

LFrin
Novice
115 Views

Thanks for your answer, I asked the question wrong.

 

I do not use the PCIe Hard IP Blocks, therefore the question is: If the speed of the transceiver channels next to unused PCIe Hard IP Blocks is limited? I'm afraid I can't use these channels as 5 Gbps transceivers.

 

 

SengKok_L_Intel
Moderator
115 Views

The key concern is the CMU PLL, if you don't use it for PCIe Hard IP,  I don't see there is a limitation.

 

Regards -SK ​

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