Speed grade, and maximum frequency?

[Altera_Forum]

Hello, 

 I am working with a Cyclone 2, speed grade 8.  According with this speed grade the maximum frequency is 125 MHz.  Questions:  1. Why the manual of CYCLONE, says that the M4K has a maximum frequency of 250 MHz, what about the speed grade?.  2. Can I access to an External SRAM at 160 MHz, although the speed grade is 8 (125 MHz)?, in the manual is specified that if I use COL I/O I can access at a maximum freq of 167 MHz, again what about the speed grade?  3. What is the difference between COL i/O and ROW i/O, how it is mapped?   Thank you,  Cordially,  Diego Botero

[Altera_Forum]

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[Altera_Forum]

I would prefer to know it,too.

[Altera_Forum]

--- Quote Start ---  ??????????  --- Quote End ---    Hi dbotero,  where does the 125Mhz coming from ????   The clock speed of a design is in most cases limited by the design itself. It depends on the logic levels between the registers. Of course there is a limit, but if you look into the small project you will see the Cyclone2 speed 8 runs much faster ! BTW: that is wors-case!  Kind regards  GPK

[Altera_Forum]

thanks for your reply! 

and what does the "speed grade -8" exactly means?

[Altera_Forum]

--- Quote Start ---  thanks for your reply! and what does the "speed grade -8" exactly means?  --- Quote End ---    Hi,  in the old PLD times it was the propagation delay from an input pin to non-registered output. I'm not sure whether this is also valid for an FPGA.   Kind regards  GPK

[Altera_Forum]

Hello 

 Somewhere I had found that the definition of speed grade was the nanoseconds propagation delay.  I believed that if the speed grade is 8, it means 8 nseconds of propagation delay, and  1/8nseconds=125 MHz, But I was wrong.  Now I am working with the same Cyclone2 speed grade 8, and according with the tool of Quartus "Timing Analyzer", my design works up to 190MHz.  You are right the maximum frequency depends of the way you design.  Att.  Diego Botero