I'm using the State Machine Wizard (Quartus II v13.1) and need help with the Transitions tab. What do I put under the "Transition (In Verilog or VHDL 'OTHERS')" column for requiring one full clock cycle to occur before proceeding to the next state? Also, what should be written for requiring an input 8 bit signal to change (to any other value) before proceeding to the next state?
Does any written tutorial exist from Altera/Intel for using the State Machine Wizard? Third party YouTube videos are better than nothing but detailed instructions would be more helpful.
Thanks.
