Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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19984 Discussions

Stratix 10 generating square wave on L-Tile Transceiver Native PHY


I am trying to generate a square wave on a Stratix 10 GXB pin.


I have instantiated an "L-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP" with the following settings:


Transceiver configuration rules: Basic/Custom (Standard PCS)

PMA configuration rules: basic

Transceiver mode: TX Simplex

Data rate: 1008 Mbps

TX local clock division factor: 4

Standard PCS/PMA interface width: 10


I have set the parallel data port to a constant vector of "0000011111"


The IP Parameter Editor has a note indicating that I need to configure my TX PLL IP to 2016.0 Mhz, which I have done. I have also instantiated and connected the Phy Reset Controller. All status signals look good (PLL locked, and "tx_ready").


With these settings, I would expect a square wave with frequency: 1008/4/10 = 25.2 MHz. However, I am measuring about 100 MHz on the o-scope.

It seems like the /4 division factor is not going into effect: 1008/10 = 100.8 MHz.


This is what the "Details" page says about "Tx local clock divison factor":


Specifies the TX serial clock division factor. The transceiver has the ability to further divide the TX serial clock from the TX PLL before use. This parameter specifies the division factor to use. Example: A PLL data rate of "10000 Mbps" and a local division factor of 8 results in a channel data rate of "1250 Mbps"


Is my understanding correct about this IP? Shouldn't I see a 25.2 MHz?

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3 Replies




As I understand it, you have some inquiries related to the tx local clock divider. 


For your information, the TX local clock divider is not dividing the serial output data rate. Instead, it is dividing the serial clock fed from the TX PLL. This allows you to use a single TX PLL to drive different channels running at data rate in division of 2 from the base. For example, using a PLL running for 10000Mbps, you can also use the same PLL to drive channels at 5000Mbps (division of 2), 2500Mbps (division of 4) and 1250Mbps (division of 8). This helps to save the PLL resources.


Please let me know if there is any confusion with my explanation. Thank you. 


I think I understand now. Your post and the "details" description of this field is very poorly worded, making it confusing and ambiguous.


The quote from the IP generator help says "Example: A PLL data rate of "10000 Mbps" and a local division factor of 8 results in a channel data rate of "1250 Mbps." I don't think this is technically wrong, but it does make it seem like the channel data rate is calculated and derived based on this setting ("results in"), when in reality it adjusts the required input clock frequency from a PLL, and the channel data rate will still be whatever you typed into the "Data Rate" field. Maybe this would be more clear:


"The TX local clock division factor adjusts the required PLL clock frequency value needed to achieve the specified channel data rate."


I guess another point of confusion is that I have never heard a PLL output defined in terms of "Mbps". Isn't the output of a PLL just a clock? Aren't clocks usually defined in terms of Hz?







Sorry for the delay. I might have overlooked the email notification of your latest post. Sorry for the confusion caused by the IP description.


Regarding the PLL output, yes, you are right, the output of PLL would be in Hz instead of Mbps. Based on my understanding, the IP is describing in term of Mbps to ease the user to know the target data rate without the need to derive from Hz.


Please let me know if there is any concern. Thank you.