Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19208 Discussions

Stratix 10 timing analysis

Altera_Forum
Honored Contributor II
1,639 Views

Hi everyone - I'm in the process of porting an Arria 10 design to Stratix 10 and have gotten a bit confused by the new TimeQuest results in Quartus 17.1. Can anyone explain the difference between the Slow 900mV corner and the Slow vid2 corner? Why isn't there a Fast vid2 corner? Can I control whether the device is running on 900mV or the vid2 voltage, or is this a board-level design choice? 

 

If it's controllable, I'd really like to just use the vid2 option as mu fmax numbers are substantially better for that corner but so far I've found the documentation to not be overly helpful with explaining what's going on here... 

 

Thanks, 

Andy
0 Kudos
5 Replies
AndyN
New Contributor I
181 Views

Hi folks - I asked this on the old forum but no-one chimed in. Hopefully now that Intel support are active on this forum, someone can cast some light...

 

Thanks,

Andy

AndyN
New Contributor I
181 Views

@mteh - I saw you in another conversation looking over unanswered questions. Care to chime in?

 

Thanks,

Andy

GuaBin_N_Intel
Employee
181 Views

There would have VID2 slow corner when you select S10 ​with -V device. This is to support lower power smartVID feature https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-pwr.pd..., section 2.2.1.

AndyN
New Contributor I
181 Views

Thanks for the reply. So this is a board design issue? if you have a -V part but it's just connected to a normal 900mV supply, you can just ignore those two corners?

 

I'm still not sure I understand how you don't need to analyze the fast vid2 corners - are they strictly "inside" the 900mV corners?

 

Thanks,

Andy

GuaBin_N_Intel
Employee
181 Views

No, it is not an board issue. If not going to use the SmartVID (programmable voltage) ,  it is supposed that we can ignore those two VID timing corners . Nevertheless, those corners should be more optimistic than 900mV which means that if you can pass the timing in normal corner, it should pass the VID corner as well.

Reply