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Stratix DSP kits 1S25

Altera_Forum
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Attached please find an example implementation of NIOS II running on the Stratix DSP kit Standard 1S25 version. 

To fully exploit it you also need the code published in stratix dsp kits 1s25 and 1s80 (http://www.niosforum.com/forum/index.php?act=st&f=15&t=1405). With this you can program the flash from the nios IDE. The example also includes pin-assignments to most of the pins on the board. Look in the TCL files. Edit the file to your likings, open a tcl console and type source filename.tcl to apply the settings.  

In addition the example implements and uses the floating point custom instructions published by M. Paolini in floating point 1 (http://www.niosforum.com/forum/index.php?act=st&f=15&t=700) and floating point 2 (http://www.niosforum.com/forum/index.php?act=st&f=15&t=699

 

The example boots from flash, and executes out of ssram's C and D. Ssram A, B are tested using memory read-writes in a rather simple manner, and also via a DMA transfer. Note that this test is not 100% bullit proff. For instance the byte lane confusion present on the stratix dsp 1s80 board will not be found using this test! 

Executing or dma'ing out of the ram puts maximum stress on the ram, as it generates rapid access cycles. 

 

The hex display is used to display loop count information. In the pio-out register I use a small trick which simplies software design: Implement PIO-OUT as a bidir register. In this way you can read-back the value most recently written, masked to the data width in question. This can often avoid the tedious task of keeping mirror registers updated using software. A task which is further complicated if you also have to keep account of bits which are not implemented in the PIO. 

 

The 4 SSRAM chips are grouped in two banks of 1MBytes (256k DWORDS) each. SSRAM_AB and SSRAM_CD. 

Advice on the ssram interface: In SOPC use the legacy components->interface to user logic and import the file ssram1.vhd. 

Prepare the interfaces as avalon requires. See ssram1.vhd comments for which signal-goes-where information.  

Set the timing to 1 setup, 2 wait and 1 hold cycles. 

I tried to use the component editor to make the ssram component but did not succeed to get the timing parameters set correctly, so you will have to do with this. 

 

Advice on the flash interface: When building it in SOPC, simply use the device te28f320j3a-110 word mode. Its compatible with the flash on the stratix std 1s25 board. To access from your program in read-mode is straight forward. Just read it as any rom/ram using a pointer for instance. To erase and program, there are examples in the nios kit installation. One is for testing flash. Copy and paste from that. The flash is CFI compliant. 

 

Have fun, but there is no WARRENTY, USE IT AT YOUR OWN RISK 

 

Comments and questions are welcome,
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Altera_Forum
Honored Contributor II
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Forgot to write that the RS232 port is set at 115200 baud.

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Altera_Forum
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--- Quote Start ---  

originally posted by larsen@Apr 22 2005, 01:11 PM 

attached please find an example implementation of nios ii running on the stratix dsp kit standard 1s25 version. 

to fully exploit it you also need the code published in stratix dsp kits 1s25 and 1s80 (http://www.niosforum.com/forum/index.php?act=st&f=15&t=1405). with this you can program the flash from the nios ide. the example also includes pin-assignments to most of the pins on the board. look in the tcl files. edit the file to your likings, open a tcl console and type source filename.tcl to apply the settings.  

in addition the example implements and uses the floating point custom instructions published by m. paolini in floating point 1 (http://www.niosforum.com/forum/index.php?act=st&f=15&t=700) and floating point 2 (http://www.niosforum.com/forum/index.php?act=st&f=15&t=699

 

the example boots from flash, and executes out of ssram's c and d. ssram a, b are tested using memory read-writes in a rather simple manner, and also via a dma transfer. note that this test is not 100% bullit proff. for instance the byte lane confusion present on the stratix dsp 1s80 board will not be found using this test! 

executing or dma'ing out of the ram puts maximum stress on the ram, as it generates rapid access cycles. 

 

the hex display is used to display loop count information. in the pio-out register i use a small trick which simplies software design: implement pio-out as a bidir register. in this way you can read-back the value most recently written, masked to the data width in question. this can often avoid the tedious task of keeping mirror registers updated using software. a task which is further complicated if you also have to keep account of bits which are not implemented in the pio. 

 

the 4 ssram chips are grouped in two banks of 1mbytes (256k dwords) each. ssram_ab and ssram_cd. 

advice on the ssram interface: in sopc use the legacy components->interface to user logic and import the file ssram1.vhd. 

prepare the interfaces as avalon requires. see ssram1.vhd comments for which signal-goes-where information.  

set the timing to 1 setup, 2 wait and 1 hold cycles. 

i tried to use the component editor to make the ssram component  but did not succeed to get the timing parameters set correctly, so you will have to do with this. 

 

advice on the flash interface: when building it in sopc, simply use the device te28f320j3a-110 word mode. its compatible with the flash on the stratix std 1s25 board. to access from your program in read-mode is straight forward. just read it as any rom/ram using a pointer for instance. to erase and program, there are examples in the nios kit installation. one is for testing flash. copy and paste from that. the flash is cfi compliant. 

 

have fun, but there is no warrenty, use it at your own risk 

 

comments and questions are welcome, 

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--- quote end ---  

 

--- Quote End ---  

 

 

 

Hello  

 

I have a problem with the DSP board 2C35  

I can&#39;t connect ssram with my nios  

the ssram is a CY7C1360B from cypress, like the the CY7C1380C from the nios board 2C35 

 

I don&#39;t anderstand how connect the address bus 

 

Do you have a solution ? 

 

thanks 

 

Passcal
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