Stratix II PLL and crossing clock domains

[Altera_Forum]

Hi, 

  I want to transfer data between two clock domains(12 MHz to 20 MHz).  I am using a Stratix II FPGA PLL to generate both clocks from a 100 MHz clock.  I need that the first rising edge of both clocks happens at the "same time", in order that a t_h and t_su violation does not happen.  How i can configure the PLL?.   The input data length is 48 and the output data length is 80, so time duration of both frames is 4 us.  Thanks

[Altera_Forum]

Your 2 clocks will have coincident edges every 15th clock of the 12MHz domain and every 30th clock of the 20MHz domain. 

 Your task therefore would be to determine when this coincidence occurs using a phase detector of your own design. You would then provide a clock enable in each of the domains on the clock cycle prior to the coincident edge.  I have no idea how you could constrain your timing so that the analyzer wouldn't flag a timing violation. I usually set false paths between clock domains and design the logic so as to avoid a violation.  This is not a standard way to cross clock domains. Have you considered using a dual-clock FIFO?  Jake

[Altera_Forum]

I don't understand from your post, which kind of data transmission is intended. At first view, it look like a parallel transmission, as jakobjones expects, when suggesting a FIFO. 

 This sentence however seems to indicate a serial transmission:   --- Quote Start ---  The input data length is 48 and the output data length is 80, so time duration of both frames is 4 us.  --- Quote End ---    In this case, simply the common 4 MHz clock could be used as a frame sync., generated from the PLL together with 12 and 20 MHzl.  Apart from these considerations, that try to utilize the integer clock ratio, they can be simple treated as unrelated, using common cross domain transfer techniques.

[Altera_Forum]

I need to pass 48 (14 bit each) symbols at 12 MHZ from a QPSK mapper, to 64 (14 bit each) subcarriers at 20 MHz as input to an IFFT. Including the GI, output frame has a length of 80 

 80/20MHz=48/12MHz= 4 us.  I'm using this in a personal OFDM processor project.  I only need synchronize both clocks (align first rising edge) in order to clock two counters (mod 48 and mod 80).  How can i detect the moment in that the two clock rising edges are aligned? How to implement this phase detector using the stratix ii embeded PLLs?   Thanks

[Altera_Forum]

As I said. By defining a 4 MHz clock in the same PLL. Each edge of it is aligned with both other clocks. All PLL clocks (with zero phase shift) are initially aligned at a PLL reset.

[Altera_Forum]

OK, it works!!!.  

 Thanks a lot FvM.