Stratix III DPA lock behaviour

[Altera_Forum]

Hello, 

 I've got some questions regarding the lock behaviour of Stratix III alt_lvds blocks (with internal PLL):  1. Simulation: Simulating these blocks shows that the DPA lock pin is asserted right after the the block's reset is deasserted (no high low transitions in receiver input!). Is this a general misbehaviour of the simulation model?  2. In hardware: Setting up a small testdesign with a loopback outside the FPGA (with coax cables) shows that the DPA circuit also locks if the receiver inputs are tied to ground (LVDS: positive and negative input tied to ground) and no transitions occur on the input pins. Is this behaviour really correct? Could anyone of you confirm this?  Based on these two questions: How can I be sure that the DPA circuitry is really correctly locked?  kind regards, emanuel

[Altera_Forum]

I didn't use Stratix III, about Stratix II and Arria DPA I know this: DPA can only work , if the input signal has edges. If this isn't guaranteed, the DPA operation should be halted. For an undriven LVDS input, the locked signal is meaningless, but not necessarily zero. I don't expect, that Stratix III is behaving basically different. 

 The Stratix III handbook tells:  --- Quote Start ---  The rx_dpa_locked signal only indicates an initial DPA lock condition to the optimum phase after power up or reset. You must not use the rx_dpa_locked signal to validate the integrity of the LVDS link.  --- Quote End ---    With a real input signal, I always experienced a considerable lock time. The handbook specifies an upper limit.

[Altera_Forum]

Alright thx for your quick reply, but the issue i experienced in my simulation does not really match the real world model at all.

[Altera_Forum]

I didn't use simulation for DPA and can't say, if it's meaningfull at all. I basically answered point 2.