Stratix-IV DXAUI

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Stratix-IV DXAUI

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Hi,

we are going to use a Stratix-IV EP4SGX230KF40C device, and I want to use the 20GbE DXAUI core.

Two questions:

- what is the required frequency of the external reference clock? Still 156.25MHz or 312.5MHz?

- how do I connect the clock signals on the XGMII-side? There is a new signal, called "tx_clk312_5", that

there is no documentation on how to use.

Thanks a lot

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