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Those of you using Stratix IV GX in a new design are no doubt aware by now of the bug Altera discovered in their production silicon:
http://www.altera.com/literature/es/es_stratixiv_gx.pdf A bit embarrassing for Altera and concerning for users. The bug requires that VCC be fully powered before VCCAUX begins to ramp. Not that anybody necessarily needs help but I thought I'd post the little circuit I devised for detecting a power-up on the 0.9V VCC rail. I then use the output of this circuit to enable my linear regulator which supplies (among other things) VCCAUX. Just thought somebody might find it useful. JakeLink Copied
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