Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20803 Discussions

Stratix IV GX transceivers: 32-bit word alignment in basic mode?

Altera_Forum
Honored Contributor II
2,290 Views

Hi. 

 

I'm working on the transceivers of a Stratix IV GX series FPGA. The handbook covers word alignment quite well for smaller data widths (e.g. 8, 16), but is vague when it comes to word alignment of 32-bit data. 

 

The BYTE alignment works perfectly, but 4 bytes transmitted (e.g. x"123456BC" turn up on the receive side in 2 consecutive words: the 2 LS bytes in received word A, the 2 MS bytes in received word B: 

 

A  

xx xx 56 BC 

 

12 34 xx xx 

 

It seems word alignment of 32 bits (in basic mode) is simply not supported (by the ALTGX megafunction), which means I have to do the word alignment myself. 

 

Have I hereby answered my own question, or am I missing something here? 

 

 

 

[p.s. Admins: the post editor auto removes spaces, making it hard for me to 'draw' signals etc in text. Can this be solved?]
0 Kudos
9 Replies
Altera_Forum
Honored Contributor II
1,244 Views

I just found a section in the handbook covering an optional byte ordering block (page 1-91, vol. 2), seems just what I need for this application.

0 Kudos
Altera_Forum
Honored Contributor II
1,244 Views

Next problem:  

 

The byte ordering block can only be used when I select a 20-bit word alignment pattern length in the Word Aligner tab (instead of the 10 bit alignment pattern I now use). However, a 20-bit pattern is not recognized as a control code, and therefore I cannot align to a 20-bit pattern (rx_patterndetect never goes high). 

 

So eventhough I can now use the byte ordering block, it it still useless because now the byte alignment does not work anymore. 

 

Are there standard 20-bit control codes, equivalent to the 10-bit K28.5 alignment code 0101111100 (which is BC decoded to 8 bits)?
0 Kudos
Altera_Forum
Honored Contributor II
1,244 Views

Fixed it - if anyone's interested in the solution, reply here or pass me a message...

0 Kudos
Altera_Forum
Honored Contributor II
1,244 Views

Hi, 

What was the issue you were seeing when using the byte ordering block? 

Can you please explain further? 

Thanks, 

M
0 Kudos
Altera_Forum
Honored Contributor II
1,244 Views

Hi, 

 

I'm working in this issue without success. Could you send me any code for synchronization? thanks, 

 

Fer,
0 Kudos
Altera_Forum
Honored Contributor II
1,244 Views

Hi! 

 

Could you please tell me the solution concerning the Word Aligner in transceiver channels of stratix iv devices? 

What is the problem in 'Basic double width' mode? 

 

Thanks
0 Kudos
Altera_Forum
Honored Contributor II
1,244 Views

Hi, 

 

I've got a similar issue. 

But instead of your example my byte-ordering looks like this: 

 

34 45 78 xx 

 

xx xx xx 12 

 

Could you send me your solution? 

I hope it will work in my case too. 

 

Thanks, 

Stefan
0 Kudos
Altera_Forum
Honored Contributor II
1,244 Views

Hi, 

 

I'm using the following alignment pattern: 

 

0x0000BC1C 

 

BC and 1C are both 8/10b control bytes. 

 

In the megafunction, I'm using the following settings: 

 

-Basic mode 

-32 bits 

-8/10 endoding (obviously) 

-Manual word alignment mode (assert the rx_enapatternalign when you know the RX is receiving the alignment pattern) 

-Word alignment pattern is 20 bits 

-Word alignment pattern: 01011111000010111100 (= 0x5F0BC)  

 

Note: The alignment pattern is entered in the megafunction in its 10/8 encoded form, so 0xBC1C becomes 0x5F0BC. 

 

-In addition, I use a byte ordering block (based on the syncstatus signal of the word aligner) that triggers on the last 1C of 0xBC1C.  

As this 1C will be encoded as a control word, I entered 000000000 100011100 as byte ordering pattern where 00011100 is 0x1C and the preceding b'1 is the control_detect flag bit. 

 

So, to summarize, I put 0x0000BC1C on the 32-bit TX user data bus where the 0xBC1C portion is 10/8 encoded as control bytes (assert tx_ctrlenable to do this) and transmitted as 0x5F0BC. The RX side word aligns to this (when rx_enapatternalign is asserted) pattern and performs byte ordering using the last 0x1C. The I put my user data on the parallel TX bus and it shows up correctly on the RX side. 

 

p.s. - I assume the transceiver is initialized properly; that the analog and digital resets are released in the correct order and based on the pll_locked and rx_freqlocked outputs etc., as described in the handbook)
0 Kudos
AVija7
Novice
1,244 Views

i have followed all these steps, but was not able to get the data in the correct order?

how you gave your  rx_enapatternalign signal and what about the rx_enabyteord?

0 Kudos
Reply