Stratix IV Hold Violations....

[Altera_Forum]

... between register A and B. Both Registers are fed by a Global Clock. Source Register and Latch Register are in adjacent labs. The problem seems to be coming from Register A being of type "ALM Register" while Register B is of type "ALM LUT Register". I have told the tool to not fix hold timing to determine how many of these paths I have. The fan out of the Global clock is ~200k so there are thousands of them. When i tell the tool to fix the hold violations it complains that there are too many of them and then screws up my setup timing. Anyone have any ideas of how to address or even some insight. 

 Thanks

[Altera_Forum]

How many LUT_REGs are being created? Open the Fitter Report -> Resource Section and it should be the ~4th row. These are created as a matter of last resort, when running out of regular registers, so most designs have 0. 

They are slower registers since they're made from LUTs, and have larger micro setup/hold times. That being said, there shouldn't be that many, and the router does not have to add much delay to meet the hold requirements, so I'm really surprised enabling hold timing is causing this. Are you sure nothing else is creating positive hold requirements in the design?

[Altera_Forum]

-- Combinational ALUTs 252,121 / 424,960 ( 59 % )  

ALUTs Used 267,397 / 424,960 ( 63 % )  Memory ALUTs 7,522 / 212,480 ( 4 % )   Dedicated logic registers 292,171 / 424,960 ( 69 % )  LUT_REGs 7,754 / 424,960 ( 2 % )  It doesn't seem that they are being called as a matter of last resort. Above report is from the fitter. The synthesis reports shows 0 so the fitter is mapping them to the LUT_REG. To me, it seems the fitter is making a bad decision about inferring these.  When I tell the tool to fix the hold times, I see a lot of very bad setup violations (500 ps to 1000 ps). When I tell the tool to NOT fix hold I see no setup violations (positive setup of a 200+ ps). If the tool would not map the logic to the LUT_REG it appears that my hold violations would go away.  I miss the old days when hold time was guaranteed by device construction (delay from LUT/REG to LUT/REG was guaranteed when source and destination where in the same clock domain).

[Altera_Forum]

Nowadays even without LUT_REGs, it's not guaranteed, i.e. the router sometimes has to add delays. By last resort, that doesn't mean you're at 100% of dedicated logic registers, as a lot of them become unavailable as all the inputs might be feeding the LUT before it, for example, or the control signals for the LAB don't match what you need.  

I've looked into it, and don't know of anyway to disable LUT_REGs, but the cases I was looking for it was told it would pretty much be a no-fit, so it wasn't a good choice. What does your average and peak routing utilization go betwee(i.e. when having it on and when having it off)? When off, are the hold violations only to/from LUT_REGs?