Stratix Ii Gx And Alt2gxb Ip

[Altera_Forum]

Hello, 

 I'am new on FPGA and I have some questions.  I try to implement the alt2gxb ip on a stratix II gx.  here all is ok.  In my design I receive datas from an optical fiber with two signals (RXN and RXP).  how can I configure my IP?   I must use 2 inputs (rx_datain[1..0]) ?  I need help because I don't know how to use differential input for my transceiver.  thanks

[Altera_Forum]

Hello, 

 I understand that you are using an optical receiver with a single ended output, that you want to interface with GXB transceiver input. If the other signal parameters are met (data rate, DC balanced signal, an appropriate reference clock available) this should basically work. The input parameters for GXB receiver are given in datasheet (common mode range, signal level, possible termination variants) you have to adapt the receiver modules output. It's necessary to connect both terminals of differential input, but I think, it could be driven by a single ended signal. At mimimum the unconnected pin should be bypassed to optical receiver signal ground with a capacitor.  Regards, Frank

[Altera_Forum]

ok my Ip is already configurated in basic mode and only as receiver. 

But in my top level I've got two signals that I received from my optical fiber RXn and RXp. So I must map this signal on receiver channel. But I would like to know if physical this inputs are mapped to rx_datain signal of the alt2gxb.  I must use my receiver input into differential input.   thanks for your response.

[Altera_Forum]

Hello, 

 I first understood, that you have single ended signal input signal, which would be unlikely for gigagbit datarate. In your HDL design, you need only an single input port per GXB channel that is connected connected to GXB rx_datain. As you assign a differential IO standard to this input in pin planner or assignment editor, you get two phsysical pins for one logical signal.  Regards, Frank

[Altera_Forum]

--- Quote Start ---  Hello,  I first understood, that you have single ended signal input signal, which would be unlikely for gigagbit datarate. In your HDL design, you need only an single input port per GXB channel that is connected connected to GXB rx_datain. As you assign a differential IO standard to this input in pin planner or assignment editor, you get two phsysical pins for one logical signal.  Regards, Frank  --- Quote End ---    thanks for your response I understand better now. But in my VHDL top level I've got two signals (from optical fiber) and only one rx_datain. I'am a few disappointed because I must assign only one rx_data signal. Have you got a solution to my probleme.  In my VHDL I use several entity and I must make the interconection in the top level. The GXB is not the top level of my design. If you want I can post my top level ?   thanks a lot for your help

[Altera_Forum]

I dont know your receiver device, but if it has RXN and RXP signals, I would regard this as differential output that could be connected to GXB differential input (assuming the signal level, termination etc. are suitable). In the HDL design, this signal should be represented by a single rx_datain input port, that could be connected to GXB transceiver instance.

[Altera_Forum]

ok thanks a lot, I think the best solution testing my design, and compil my project. 

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