Stratix V Hard IP PCIe, Timing Errors

[Altera_Forum]

Hi, 

 I have been building a system around the Avalon-ST version of the PCIe Hard-IP for Stratix V. Specifically I am using the Gen3x8 variety.  It is happily working away and I can get data transferred between windows (KMDF driver) and the board and vice-versa, so no problems there.  The trouble is that every time I compile the design I end up with a set of timing errors in timequest that I can't seem to be rid of. To make things more of a pain, each time I compile it, some of them vanish, others appear, sometimes there are none. What they all have in common is the following nodes:  *|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~O_OBSERVABLESYNCPLD *|altpcie_sv_hip_ast_hwtcl:pcie_interface|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip~SYNC_DATA_REG## (where the# # is some number e.g. 44, 57, etc)  Usually there are a handful of these errors with slacks or anywhere from a few picoseconds, to a few hundred picoseconds - which sounds like very little, but actually that as high as 10% of the clock period.  Now as they are coming from inside the PCIe IP core, I have no idea where those nodes are, what paths data takes, and how they relate to my design.  For the last few months I have just been ignoring them and everything seems to be working fine, but that makes me uneasy - i don't like just ignoring things and hoping they go away. I have no idea whether they aren't causing a problem because they either aren't an issue, or because the FPGA I am using (5SGSMD5K2F40C2N on this: http://www.altera.co.uk/products/devkits/altera/kit-stratix-v-dsp.html) just so happens to be running in one of the more optimistic corners of the timing model when these paths do meet timing.  To try and get an idea of how important they are, I set some false paths just to see what the effect was, and the whole thing stopped working (after removing the constraints it became apparent that these paths were missing timing by a looooong way, in all corners of the model). That seems to suggest that they are something I need to worry about.   I've tried searching the web for any reference of these particular nodes, but have found nothing. The question then, is it safe to ignore these? or is there a timing constraint I am missing somewhere? Or is there something I can do to help make the design meet timing?  Thanks in advance.

[Altera_Forum]

Well, still no idea about where the errors are coming from, but I've created a logic lock region for my application layer partition and compressed it as much as possible into on corner next to the PCIe transceivers and the errors have vanished. Problem solved I guess.

[Altera_Forum]

The Altera forum is maintained by users, rather than Altera directly. I'd recommend filing a Service Request with Altera and asking their advice. 

 I agree that its disconcerting when black-box IP does not meet timing, given that you have no idea what is wrong or how to fix it!  Your logic-lock solution seems to be a good work-around, but I'd argue that if Quartus can meet timing in that situation, then based on meeting the IP timing constraints it should have placed the logic that close together without the user having to add a logic-lock region!  Please post the response to your Service Request if you learn something useful :)  Cheers, Dave