Hello. I hope some one here can help.
I have a Stratix-V GX device that has 6 transceivers in a bank. I want to use all 6. The 6 channels will be independent. Each will transmit at the same rate (2.488 Gbps). The 6 receivers will each recover an independent line clock. I am using the Native PHY core. I also have a Reconfiguration core and a Reset control core as per recommendation. When I limit the design to 4 channels instead of 6 I can get it working. When I change up to 6 channels the tool reports an error that I don't have enough clocks. I understand the reason is that I need to instantiate an ATX PLL. What I need to know is which cores exactly must I use to get this working and how should they be interconnected.
Anyone here know about these things?
- John
