Stratix10 Global Clock assignment is ignored

[mappy5]

I'm trying to synthesize an IP using virtual pins.

The Clock signal of the virtual pin is directly connected to the IP.

Global Signal ON is set in the assignment editor for the clock of the virtual pin.

However, when I check the list of Use clock options in the Timing Optimization Advisor, the Global Resource Used for the clock signal is No.

There is no Global Clock synthetic Warning or Warning for Clock signals in the log.

When I tried it with Arria10 in the same way, I was able to assign it to the Global Clock in Arria10.

How can I assign a Clock to a Global Clock in Stratix 10?

• Quartus Version : Pro 20.3.0 Build 158

[SyafieqS]

Global Signal assignments only controls whether a signal is promoted using the specified dedicated resources or not, but does not control which or how many resources are used.

To take full advantage of the routing resources in a design, make sure that the sources of clock signals (input clock pins or internally-generated clocks) drive only the clock input ports of registers

[mappy5]

Hi SyafieqS_intel,

Will assigning a virtual pin to a dedicated CLK pin solve the problem?

Is the GCLK allocation method different between Stratix10 and Arria10 due to the difference in clock resources?

[SyafieqS]

Yes, Stratix 10 and Arria 10 have different architecture and clock network. 

[SyafieqS]

May I know if there is any update?