Stratix4 decoupling capacitor for all the power net

[Altera_Forum]

Hi, 

 Now I'm using the Stratix4 (EP4SGX230) to do my design, but in the handbook, I just find the on-Package decoupling capacitor information, but there is no information about the On-Board decoupling capacitor information, I need this information when I start to do the circuit design, where I can find them.  By the way, I also need to choose the power chips for the FPGA, whether there is a document to explain the max current for the core power.   Best regards, YeXian

[Altera_Forum]

You shouldn't need the detail of the on-board decoupling capacitors to do your circuit design, only the recommended board decoupling, for a particular family. See "an 574: printed circuit board power [pcb] delivery network [pdn] design methodology (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an574.pdf)" for starters. 

 I also suggest you look at the schematics of a suitable stratix iv development board (https://www.altera.com/products/boards_and_kits/all-development-kits.html#stratix-iv) to see what Altera have done.  The "powerplay early power estimators (epe) and power analyzer (https://www.altera.com/support/support-resources/operation-and-testing/power/pow-powerplay.html)" spreadsheets will help you determine how much power each rail of your FPGA will take.  Cheers, Alex