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Hi,
I had generated Stratix5 PLL (s5_pll) using Megawizard Plugin and the created pll instance is pll_test_0002 with a top level wrapper arouND IT. tHE GENERATED FILE IS SHOWN BELOW;module pll_test (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire locked, // locked.export
output wire outclk_0, // outclk0.clk
output wire outclk_1 // outclk1.clk
);
pll_test_0002 pll_test_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.locked (locked), // locked.export
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1) // outclk1.clk
);
endmodule
Now i have a top level instance top.v with instance pll_test along with some sub-modules. While synthesis in Quartus, toll gives below error; -------------------------------------------------------------- Error (12006): Node instance "s5_pll_inst" instantiates undefined entity "s5_pll_0002" Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 0 warnings -------------------------------------------------------------- This error indicates, s5_pll_0002 (generated by Megawizard), Quartus tool is not able to identify. Please guide me to get rid of this error. Regards, freak
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what release are you using? i recommend the latest when targeting SV
that said i have successfully compiled SV designs that include PLLs- Mark as New
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Hi,
This is a VERILOG code. I am using 11.2 Quartus release. Please guide. Regards, freak- Mark as New
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Do you see the qip file in the design files.?
there should be a pointer to the sub files in the mega-function directory that will include the pll_test_0002 file- Mark as New
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Hi connollytr,
Thanks for your input. You were little late :) I got this file few days before and things are working... Thanks u all !! Regards, Jaseel
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