Suggestions for simple link between two FPGAs?

[Altera_Forum]

I need to transfer about 100 bytes of data between two Cyclone IV GX FPGAs on two different PCBs. The PCBs are pretty close (less than 6 inches/15 cm) and the hardware hasn't been designed yet, but I don't want to use loads of interconnect. Can anyone suggest a simple link that I can use?

[Altera_Forum]

The most simple and fastest link is parallel bus. E.g. 8 bit wide bus + clock + additional signals if needed (valid, start, stop, etc..). The most common and simplest is SPI. Great speed and easy to implement.

[Altera_Forum]

A parallel bus uses loads of interconnect, so I was favouring something serial. SPI is too slow as I need about 10MBytes/sec. I think a serdes pair and LVDS may be the way forward.

[Altera_Forum]

SPI is definitely not too slow. It is simple packet serialization engine. You can run SPI between FPGAs even @ 100MBytes/s... Think of the SPI implementation, not the SPI protocol itself.

[Altera_Forum]

I'll have a think about SPI speed. Do you really think 100MBytes/sec is simple in hardware as I make that 800MHz.

[Altera_Forum]

Yes, SPI should would nicely without using that much I/O. 

 SERDES would just be excessive for a mere 10Mby/s rate, unless you know you're going to use a XCVR equipped part, AND have an unused channel. Using a SERDES XCVR would be, to me, using "loads of interconnect" seeing as how you only have a few available in most devices, and the cost per XCVR is pretty high.  The alternatives to SPI could be doing something like LVDS which should work fine at that distance and data rate, though you'd use more I/O due to the differential signaling. If you wanted to you could use something like a RS-422 transceiver (which will get you 10 Mbit/s) to add some ESD protection and decouple the board to board link from the FPGAs' pins, though it would be overkill for a mere 6" run, it is cheap and relatively compact.  If isolation is a concern, there are optocouplers and capacitive or inductive monolitic coupler devices from the likes of TI, A/D, etc. that will couple general digital signals which could be SPI or RS422 pre-transceiver logic level signals, or any other protocol.  LVDS is basically made for sending high speed Gb/s level (just short of SERDES realm) multiplexed data over short board-to-board distances, with low EMI and good signal integrity which is why they use it in LCD panel to controller board links, and it can commonly run up near 1Gb/s so a mere 10Mb/s is no difficulty with it, and it does not require a SERDES, or, in fact, any difficult multiplexing of the parallel data bits at that slow rate. The only real concerns would be ESD and any power / protocol sequencing issues, and implementing the framing state machine, but there are app notes for that, or any simple ad hoc encoding solution would be fine without a clock or any ad hoc framing solution if you transmit the clock distinctly (not really a worry over 6" B-B @ 10Mb/s with a decent interconnect).

[Altera_Forum]

Two LVDS pairs (clock pair and data pair) is a sensible hardware solution, but at say 100MHz the interconnects would have to be carefully designed to meet clock skew, even over 6 inches.

[Altera_Forum]

100 MBy/s (1Gb/s) isn't your requirement, you said you needed 10Mbits/sec, which is comfortable speed for something similar to SPI. 1Gb/s / 100MBy/s and for you'd be looking at RMII / GMII / SGMII types of links or add a PHY and use Gb-ethernet, or just a simpler trivial LVDS implementation for a short board to board link. 

 For a half duplex link -- (add another in reverse if you want bidirectionality). You can just use one differential LVDS pair, transmit scrambled/encoded data at 20Mb/s and do fabric (not SERDES) based sampling and CDR at the remote end like the application notes for multiplexed LVDS say.  Or send 2 differential pairs: (clk+, clk-), and (txd+, txd-), 4 wires + board-to-board GROUND, and don't worry about clock data recovery, just packet framing which could be as simple as NRZ UART mode or something like SDLC/HDLC or whatever if you prefer, nothing difficult at all.  Or if you make the protocol take turns (either via a bus grant / direction line in hardware or a logic based multiple access token ring like scheme) you could share the same physical data (and optionally clock, unless multiplexed with the data) lines for bidirectional use halving the interconnect requirements at the cost of latency and bus sharing complexity.   Other approaches might be to use the JTAG system or access the 2nd board's configuration data stream from the 1st board if you already share these connections and making use of them would be feasible to achieve your needs, it would conserve more interconnect resources and take better advantage of what you already have. You didn't say if the need was bidirectional, master/slave, one time only, or continuous transmission. Of course if the boards are on the same ethernet channel and you can inject a custom packet into that . . .     --- Quote Start ---  I'll have a think about SPI speed. Do you really think 100MBytes/sec is simple in hardware as I make that 800MHz.  --- Quote End ---  

[Altera_Forum]

Yes, clock skew and ESD are concerns, but there are impedance and frequency response controlled board to board interconnects that would make it a very sensible approach even without clock/data multiplexing and the possibility for skew. But usually at high enough rates one would just encode the data and clock and do a logic based CDR to avoid skew problems, or do some kind of synchronization / compensation anyway. 

 But for a mere 6" path @ 100 MHz you could have something that is every bit as good as a "on board" connection just by using the right board to board connectors with proper signal integrity / impedance / frequency response. For all I know you might just use a male/female PCB mount header or something to plug the boards together which would be better than even what one would consider a "backplane interconnect" to provide. Or FFC as is used with LCD LVDS or a couple SMB micro coax links or whatever. There are lots of good quanity short distance options that will not skew your signals by 50ns if you do use a clk and data distinct set @ 100Mhz.  Anyway it doesn't matter much, if 10Mhz will work for you, use 10 or 20, less EMC, less timing worries, etc.    --- Quote Start ---  Two LVDS pairs (clock pair and data pair) is a sensible hardware solution, but at say 100MHz the interconnects would have to be carefully designed to meet clock skew, even over 6 inches.  --- Quote End ---  

[Altera_Forum]

I said 10 MByte/sec, not 10 Mbit/sec, so my skew margin is 5nsec

[Altera_Forum]

--- Quote Start ---  I said 10 MByte/sec, not 10 Mbit/sec, so my skew margin is 5nsec  --- Quote End ---    My mistake, I meant to say 5, not 50. Anyway 5ns mismatch is a foot or two of cable propagation delay equivalent differential length at a reasonable impedance.   It would be hard to get signals anywhere nearly that badly mismatched in time relative to each other coming from the same small physical source over a foot or so of transmission distance using any kind of proper impedance control / termination. It shouldn't be an issue to get 100Mbit/s, and if you're worried about it you can use two data lanes at half rate instead of one, but I'd just design the interconnect properly and not worry about it.  LVDS gets used more than for that sort of speed and distance all the time.