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I am trying to develop a design that involves floating point arithmetic with DSPs in an Arria-II GX device. I would like my code to be portable so I am trying to avoid the use of MegaCores. Does anybody know if Quartus-II v11 has support for the VHDL-2008's "float_pkg" package?
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For reasonable performance, float arithmetic needs pipelined operation. It's not provided by the float package yet, I wonder if pipelining is an alien concept for the authors.
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Quartus 2 will compile it (well the VHDL 1993 compatible version)
But like FvM said, there is no pipelining support, so you better use altera's floating point IP blocks.- Mark as New
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I wonder, if there's a reasonable way to implement pipelining in a behavioral description like IEEE.float_package. It must use explicite register instances that can't be hidden in a function or operator.
As discussed previously, the Quartus synthesis has capabilties to "pull" register instances into an inferred integer divider, but the registers still need to be defined besides the "/" operator. Bu this looks like a good way for a float package implementation.- Mark as New
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The only way I could think of would be equavalent to the altera IP cores anyway. So what you really need is Quartus somehow infering the IP using the fp function followed by a shift register. But given how you cannot do this even for an integer "/", you might be waiting a while for float_pkg support. You can always do type converts from this package to SLVs in and out of the alteraFP IP, but again, this is pretty pointless if all you have is FP IP cores.
Apparently full 2008 fixed_pkg support is coming in Q12.1, so maybe they are doing something with the float package (but I highly doubt it).- Mark as New
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Hi
I have one set of floating point array, if i compare floating point array numbers with integer, like 3.6 and 3 , 3.6 should be greater..... eg: if 3.6 > 3 output<=1 How do i declare floating point array?- Mark as New
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type float_array_t is array(0 to n-1) of float32;

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