I am trying to generate a project using a Stratix V FPGA (5SGXEA7K2F40C2) to communicate with the On-board DDR3 via a loopback from QSFP+ cables (ie. the DQ, DQS, etc. signals will be sent over SMA cables connected to the QSFP+ cage). My issue right now is that I cannot find a clock that the fitter will allow me to use as the reference clock for the XCVR PHY. The reference manual for this FPGA only lists two clock frequencies, 282.5 and 644.5 MHz, as "QSFP" clocks. I am not sure why I can't just use the same reference clock for the XCVR PHY as I do for the DDR3 PHY? What rules govern what physical clocks I can use as reference clocks? I would appreciate any general information surrounding this topic or even some good literature that could help me better understand clocking and distributing clocks on an fpga... Here is the error that the fitter is giving me:Error (175006): Could not find path between source fractional PLL and the ATX PLL Error (175022): The ATX PLL could not be placed in any location to satisfy its connectivity requirements Thanks in advance for the help.