I am trying to create a synopsys design constraints file that I can use for timing.
In part of my design, I have a clock clk that goes into a PLL and as output, I get out clk x 2 (clk at twice the frequency which I call clkX2)
Then, I have a mux that selects between clkX2 and ~clk based on a mode bit.
My question is that how do I specify this in the constraints file.
This is what I have:
# Create generated clocks based on PLLs
derive_pll_clocks -use_tan_name # Here is where I define the input clock
create_clock -name vclk -period 3.0 -waveform {0 1.5} [get_ports {vclk}] # Here is where I define the invert of the input clock
create_generated_clock -name clk_inv -divide_by 1 -invert -source [get_ports vclk] [get_nets clkcrl:u2|clkout] # I am not sure about this part. Basically what I am doing is creating a generated clock which is basically the output of the PLL (which is clk x 2)# I couldn't find any other way to attribute the already generated PLL output clock to the net where it is muxed
create_generated_clock -add -name clk_x2 -divide_by 1 -source [get_nets {clkctrl:u2|clkdbler:cdb0|altpll:altpll_component|altpll_l3t1:auto_generated|clk[0]}] [get_nets clkcrl:u2|clkout] # Here I am defining an exclusive clocks group (clkX2 and ~clk) that has the 2 clocks. Only one of the two clocks is active at any given time in the design.# The example given in the altera timequest timing analyzer (@
http://www.altera.com/literature/hb/qts/qts_qii53018.pdf ) is below:# create_clock -period 40 -name clk_A [get_ports {port_A}]# create_clock -add -period 20 -name clk_B [get_ports {port_A}]# set_clock_groups -exclusive -group {clk_A} -group {clk_B}
set_clock_groups -exclusive -group {clk_inv} -group {clk_x2} Is what I am doing correct? Is there another way of doing this?
