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Valued Contributor III
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Synthesis error - RAM resource ?

Dear all, 

 

Currently I'm designing a project using Stratix IV 4SGX230N. In my design I try to implement three FIFOs (all of them are designed using MegaWizard) which resource usage are shown in these following : 

1. 1st FIFO : 45 LUT + 65536 RAM bits + 239 reg (width = 1 bit, depth = 65536) 

2. 2nd FIFO : 64 LUT + 524288 RAM bits + 255 reg (bitwidth = 4 bits, depth = 131072) 

3. 3rd FIFO : 96 LUT + 1048576 RAM bits + 257 reg (bitwidth = 8 bits, depth = 131072)  

 

When I compiled this design I got an error message like this : 

Error: Cannot place 92 RAM cells or portions of RAM cells in the design Info: The Fitter setting for Equivalent RAM and MLAB Paused Read Capabilities is currently set to Care. More RAMs may be placed in MLAB locations if a different paused read behaviour is allowed. Info: Cannot place following RAM cells or portions of RAM cells -- a legal placement which satisfies all the RAM requirements could not be found Info: Node "tserd_4sgx230_sopc:tserd_4sgx230_sopc_inst|fifio_sopcwide:the_fifio_sopcwide|fifo_sopcwide_top:fifio_sopcwide|FIFO_Wide:U_FIFO_Wide|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_r2j1:auto_generated|altsyncram_og31:fifo_ram|ram_block11a0" Info: Node "tserd_4sgx230_sopc:tserd_4sgx230_sopc_inst|fifio_sopcwide:the_fifio_sopcwide|fifo_sopcwide_top:fifio_sopcwide|FIFO_Wide:U_FIFO_Wide|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_r2j1:auto_generated|altsyncram_og31:fifo_ram|ram_block11a3" Info: Node "tserd_4sgx230_sopc:tserd_4sgx230_sopc_inst|fifio_sopcwide:the_fifio_sopcwide|fifo_sopcwide_top:fifio_sopcwide|FIFO_Wide:U_FIFO_Wide|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_r2j1:auto_generated|altsyncram_og31:fifo_ram|ram_block11a2" Info: Node "tserd_4sgx230_sopc:tserd_4sgx230_sopc_inst|fifio_sopcwide:the_fifio_sopcwide|fifo_sopcwide_top:fifio_sopcwide|FIFO_Wide:U_FIFO_Wide|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_r2j1:auto_generated|altsyncram_og31:fifo_ram|ram_block11a1" Info: Node "tserd_4sgx230_sopc:tserd_4sgx230_sopc_inst|fifio_sopcwide:the_fifio_sopcwide|fifo_sopcwide_top:fifio_sopcwide|FIFO_Wide:U_FIFO_Wide|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_r2j1:auto_generated|altsyncram_og31:fifo_ram|ram_block11a32" Info: Node "tserd_4sgx230_sopc:tserd_4sgx230_sopc_inst|fifio_sopcwide:the_fifio_sopcwide|fifo_sopcwide_top:fifio_sopcwide|FIFO_Wide:U_FIFO_Wide|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_r2j1:auto_generated|altsyncram_og31:fifo_ram|ram_block11a35" Info: Node "tserd_4sgx230_sopc:tserd_4sgx230_sopc_inst|fifio_sopcwide:the_fifio_sopcwide|fifo_sopcwide_top:fifio_sopcwide|FIFO_Wide:U_FIFO_Wide|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_r2j1:auto_generated|altsyncram_og31:fifo_ram|ram_block11a34" Info: Node "tserd_4sgx230_sopc:tserd_4sgx230_sopc_inst|fifio_sopcwide:the_fifio_sopcwide|fifo_sopcwide_top:fifio_sopcwide|FIFO_Wide:U_FIFO_Wide|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_r2j1:auto_generated|altsyncram_og31:fifo_ram|ram_block11a33" Info: Node .............. (similar error like above) .............. Error: Can't fit design in device Error: Quartus II Fitter was unsuccessful. 2 errors, 671 warnings Error: Peak virtual memory: 568 megabytes Error: Processing ended: Sun Nov 07 20:35:15 2010 Error: Elapsed time: 00:08:59 Error: Total CPU time (on all processors): 00:08:59 Error: Quartus II Full Compilation was unsuccessful. 4 errors, 991 warnings  

 

So I have some questions about this error : 

  1. Is it really that my current design can't fit to my stratix IV? When I checked the Stratix IV reference manual it is written that the total RAM bits provided by Stratix IV is 17133 Kbits which means it is big enough to store my three FIFOs requirement. :confused: 

  2. What other resources that I have to check to ensure that my design fits in my stratix IV board? 

  3. Does anyone know how to solve this problem? :( 

 

 

Looking forward to hear any suggestion from all of you guys. Thank you!
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4 Replies
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Valued Contributor III
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Re: Synthesis error - RAM resource ?

It is not as simple as calculating the number of bits you need. This figure is the totla available if all the memories are used efficiently. Im guessing you are not using them efficiently. What is your word width? most efficient is 9/18/36 bits

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Valued Contributor III
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Re: Synthesis error - RAM resource ?

Hi Tricky, thanks for your reply :) 

 

Hmm..do you mean the word width in the memory? I'm using 32 bits. How can you know that 9/18/36 bits are more efficient? 

 

Do you have any tips about how to use memory efficiently? Well, I still don't fully understand the 'efficiency' aspect in memory usage. And another question, how do we measure our memory usage efficiency? Or are there any performance parameters that represent the memory usage efficiency? 

 

Thanks
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Valued Contributor III
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Re: Synthesis error - RAM resource ?

Update : 

I found some mistakes in my FIFO depth. I have re-compiled and synthesized my design successfully. 

 

@Tricky : 

If you don't mind I'm still waiting for your explanation about memory efficiency. Thanks :)
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Valued Contributor III
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Re: Synthesis error - RAM resource ?

In stratix 4, there are 3 type of memory blocks - MLAB, M9K and M144K. Each one can hold 640, 9216 and 147456 bits respectively. There are different n words x word width configurations. For example, the M9k can be used as a 8k x 1bit, 4kx 2bit, 2k x 4bit, 1kx8 or 9bit (the 9th bit is meant for parity, but can be used for data), 512x16 or 18bit or 256 x 32 or 36 bit (4 parity bits). Because these are the only configurations, if you had a a 13 bit word, you would have to have it configured as 512x16, and you would not be able to use the last 3 + 2 parity bits (unless you had some parrallel data that could fit in there). This would mean you're wasting memory.

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