SystemVerilog Testbench

[Altera_Forum]

Hello, I'm reading the book SystemVerilog for Verfication by Spear and was wondering if anyone is using SystemVerilog for Verfication and if they had an simple example they could provide? 

 Thanks, joe

[Altera_Forum]

if someone had,please give me one copy,my email cann't post because of my posts. waiting on the forum. 

thanks in advance, kuix

[Altera_Forum]

I hope someone can help. I've been using the simulator built into Quartus so writing test benches and running ModelSim is still new. When I think of a test bench I usually see a single file but as I look into SystemVerilog Verification it mentions the Generator, the Agent, the Driver, the Monitor, checker. All of which are in separate modules and appear to be separate files too. Is that a big deal?  

 I run ModelSim from Quartus.   http://chris.spear.net/systemverilog/   The web site above has some examples that I'll try to get working.  joe

[Altera_Forum]

No, all those files are just necessary if you want to have complex testbenches based on the methodology described in that book. Other books have other methodologies, most of them with a single file and module.

[Altera_Forum]

Hello, thank everyone for your comments. Can you please tell me what simulator you are using, please include the version? 

 Thanks, joe