Help me!

Altera_Forum · ‎01-17-2010

Hi every one ! I actually wanna get your hand cause I was doing with EPM7064SLC44-10( MAX7000S) but I have problem with JTAG, I can't load it and now it makes me trouble!.. Please fix me the problem and Quartus II .. Thanks so much.. I will upload the board schematic right now!:):)

http://ifile.it/0smp31z/icao_fpga.schdoc

(http://ifile.it/0smp31z/icao_fpga.schdoc)

Altera_Forum · ‎01-17-2010

It's clearly wrong to place a pull-up resistor at TCK, a pull-down resistor is needed instead.

P.S.: Also the CLK AC coupling seems faulty, but it hopefully wouldn't block JTAG communication.

Altera_Forum · ‎01-18-2010

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It's clearly wrong to place a pull-up resistor at TCK, a pull-down resistor is needed instead.

P.S.: Also the CLK AC coupling seems faulty, but it hopefully wouldn't block JTAG communication.

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Thanks Mr FvM! I'll check the circuit board and try it again. If you have another idea, hooefully we can discuss. Thanks very much.

Altera_Forum · ‎01-18-2010

But you can spell out why TCK node is wrong??? I think TCK is the same as the others

Altera_Forum · ‎01-18-2010

Altera's guidelines recommend TCK be tied to GND through a 1K resistor.

I don't have Altium Designer and haven't looked at your schematic. However, I've found that many JTAG signal integrity problems can be solved by adding source-series termination to the JTAG signals. So for example, a 33ohm or 50ohm resistor on TCK, TDI, and TMS right at your JTAG connector. Also, a resistor on TDO coming out of the FPGA.

I'm not saying this is your issue. Usually if signal integrity is a problem, you'll at least be able to scan the chain even if only intermittently.

Jake

Altera_Forum · ‎01-19-2010

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Altera's guidelines recommend TCK be tied to GND through a 1K resistor.

I don't have Altium Designer and haven't looked at your schematic. However, I've found that many JTAG signal integrity problems can be solved by adding source-series termination to the JTAG signals. So for example, a 33ohm or 50ohm resistor on TCK, TDI, and TMS right at your JTAG connector. Also, a resistor on TDO coming out of the FPGA.

I'm not saying this is your issue. Usually if signal integrity is a problem, you'll at least be able u to scan the chain even if only intermittent.

Jake

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! Yo

Thanks Mr jacobjone! you know, my design have a problem for long time, it made me trouble so I 'll check your advice. But you can tel me how to scan the chain.....

Altera_Forum · ‎01-19-2010

Use the Quartus II Programmer.

One thing you may want to look into is the "JTAG Chain Debugger" tool. This is available from the "Processing" menu in the Quartus II Programmer window.

http://quartushelp.altera.com/9.1/mergedprojects/program/pgm/pgm_com_jtag_debugger.htm

I'm not sure when this was introduced. I just found out about it recently.

Jake