hi all,I've faced problem with one tutorial published by Altera " Testing Triple Speed Ethernet on DE2-115" ftp://18.104.22.168/up/pub/altera_material/12.0/tutorials/de2-115/using_triple_speed_ethernet.pdf After compiling the project with no error except TimeQuest (SDC) file has a problem I think it's on clocking I tried to find a solution but no way. The photo below https://www.alteraforum.com/forum/attachment.php?attachmentid=6736 Any I can't continue the rest of the tutorial specially when it comes to implement the tutorial on Altera Monitor Program https://www.alteraforum.com/forum/attachment.php?attachmentid=6737 The code below is (sdc) file which I think is the problem from it.
create_clock -period 20 derive_pll_clocks derive_clock_uncertainty set_clock_groups -exclusive -group ] -group ] -group ] -group ]Could any one please tell me a solution to this problem specially Altera not update any solution yet. Thanks in advance to all of you.
About the TQ warning you should be more specific, by reporting the actual failing paths.Anyway, from the screenshot saying 'unconstrained paths' I guess your tutorial doesn't fully constraint the design, probably I/O ports. This is a common (and bad) practice in tutorials and sample designs which avoid the full contraints for sake of simplicity and (I think) for better portability of the same design on several eval boards. However the involved frequency in such cases are quite low and usually these warnings don't affect your system operation. The message box in the second screenshot means you are using TSE core in OpenCore mode, i.e. in demo mode without a permanent licence: the core will stop working if you close that message box or detach the USB Blaster cable. Then simply DON'T press the Disconnect button and probably you will be able to successfully go on with the tutorial.
Thanks a lot Gris72,I've recheck the project again, you mentioned a good point about unconstraint input/output. The main code have problem with the following section, it is related to the Ethernet 0, and 1.
nios_system u0( .clk_clk (sys_clk), // clk.clk .reset_reset_n (core_reset_n), // reset.reset_n .tse_mac_conduit_connection_rx_control (NET1_RX_DV), // tse_mac_conduit.rx_control .tse_mac_conduit_connection_rx_clk (NET1_RX_CLK), // .rx_clk .tse_mac_conduit_connection_tx_control (NET1_TX_EN), // .tx_control .tse_mac_conduit_connection_tx_clk (tx_clk), // .tx_clk .tse_mac_conduit_connection_rgmii_out (NET1_TX_DATA), // .rgmii_out .tse_mac_conduit_connection_rgmii_in (NET1_RX_DATA), // .rgmii_in .tse_mac_conduit_connection_ena_10 (ena_10), // .ena_10 .tse_mac_conduit_connection_eth_mode (eth_mode), // .eth_mode .tse_mac_conduit_connection_mdio_in (mdio_in), // .mdio_in .tse_mac_conduit_connection_mdio_out (mdio_out), // .mdio_out .tse_mac_conduit_connection_mdc (mdc), // .mdc .tse_mac_conduit_connection_mdio_oen (mdio_oen) // .mdio_oen );What do you think the wrong on this code, is it not connected to (sopc/qsys)? or there might be some problem with the clock?