Testbench: Read from Text File

[Altera_Forum]

I have a set of test patterns in text file to be used in test bench written in verilog. test pattern will be sent to top module one by one for every posedge of clock once the ena is high. 

 Is there related function or syntax to implement the above task? Pls give some simple example. thanks

[Altera_Forum]

Depends on your testpattern format. The easiest is to use $readmemh/b and read it into a Verilog memory. More fancier approach would be to use $fopen, $fscanf/$fgets etc. 

 A quick google search for $readmem would give you some syntax to start with. We cover this in good detail during our comprehensive functional verification course.  Regards Srini cvcblr.com/blog

[Altera_Forum]

Thanks. It helps