The appropriate DDR3 topology of Cyclone V

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The appropriate DDR3 topology of Cyclone V

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Hi, all

I am now working with Cyclone V 5CEFA9 and using the hard memory controller for 32bits data width according connecting two x16bits DDR3s.

The Extermal Memory Interface Handbook tell that the Cylcone V doesn't support fly-by topology,so I wish any one can tell me what's the appropriate topology in my use?

Thanks.

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