The multiply need a cycle?

[Altera_Forum]

http://space.ednchina.com/upload/2009/5/12/156a78c3-bd54-4f18-bb84-d02fe14db28d.jpg  

 the figure above is the example of TimeQuest appnote, but the LPM_MUL gives the figure below shows there is no delay cycle when using non-pipeline multiply. Who can tell me why 2 Cycles is needed in the first image? Thanks! http://space.ednchina.com/upload/2009/5/12/18ee7731-21a1-45fd-b5d0-eb518c59b55e.jpg

[Altera_Forum]

No images.

[Altera_Forum]

can't you see the images?

[Altera_Forum]

No images above or below. 

 Anyway, if you are asking about why pipelining a mult then the answer is to break long combinatorial paths and help achieve better fmax. one or two or more pipeline stages are an option in any combinatorial paths, not just multipliers.   edit: to show the mathematical muscles:   fmax = 1/(<register to register delay> - <clock skew delay> + <micro setup delay> + <micro clock to output delay>)   hence fmax can be increased if data delay is lowered. Tsu and Tco and clk delay are to do with silicon fabrication of registers... clk delay can be made worse by the designer through gating

[Altera_Forum]

I was able to see the images by manually extracting the links. They are simply unrelated. The first image shows a multiplier with additional input and output registers, that's not the standard implementation of LPM_MULT. To my opinion, the MegaWizard dialog and explanation is very clear in this respect. The second image shows the dataflow of an unregistered multiplier, however ignoring the logic cell delays. 

 At kaz mentioned, it may be meaningful to add registers or pipeline stages in some situations. It depends on the design speed, of course. You can forget about it first and remember the option, if the timing analysis shows problems.

[Altera_Forum]

Thanks very much!